1. Field of the Invention
The present invention relates to cost efficient methods and apparatus for increasing the data bandwidth associated with dynamic memory devices and, more particularly, to methods and apparatus for increasing the data bandwidth associated with memory devices, such as dynamic random access memory (DRAM) devices, to achieve pipelined nibble mode (PNM) operation. Such methods and apparatus may also find application in the realization of synchronous dynamic random access memory (SDRAM) or other memory devices.
2. Description of the Prior Art
It is generally known that a goal in the design of memory devices, such as DRAMs and SDRAMs, as well as related control circuitry, is to provide increased memory throughput, i.e., increased data bandwidth. It is also generally known that such an increase in data bandwidth may be substantially achieved by parallelizing memory access cycles through the implementation of concurrently operating pipeline stages. However, in the past, this was only possible with considerable costs due to additional control logic/registers resulting in larger chip sizes.
In DRAM device technology, modes of operation such as hyper-page and EDO (extended data out) have been implemented in an attempt to optimize memory access cycles and thereby increase data bandwidth. Hyper-page and EDO modes of operation are essentially the same in concept and characterized by a single row address being decoded to activate a common row referred to as a xe2x80x9cpage.xe2x80x9d Activation of a page enables memory location therein to be randomly accessed (read from or written to) individually by decoding varying column addresses corresponding thereto.
Referring initially to FIG. 1, a timing diagram illustrates an example of EDO mode operation. Particularly, upon the transition of a row address strobe (RAS) signal from a high logic level (e.g., +3.3) to a low logic level (e.g., 0V), a single row address is decoded thereby activating said row (page). Next, upon the transition of a column address strobe (CAS) signal from a high logic level to a low logic level, the first column address is decoded and the data corresponding to that column address in the particular activated row (page) is read from the memory location and placed on the external data input/output (DQ) lines of the DRAM device.
If a write operation is being performed, then the selected memory location is provided with data present on the DQ lines of the memory device. Nonetheless, the next column access is received (i.e., next transition of CAS from a high logic level to a low logic level) and the next memory location is accessed in that particular row (page). Data is then either read from or written to the selected memory location in a similar manner as explained above. Such a memory access procedure continues for each occurrence of a new column address (i.e., low logic level CAS).
A time interval tAA is shown in FIG. 1 and is defined as the time interval measured from the beginning of a column address transition to the time when data is available to be externally read on the DQ lines. This time interval tAA is critical in such operational modes because, as shown in FIG. 1, the data must be available to be read by the end of this time interval or else the next column access will occur thereby destroying the data from the previous column access. A major difference between fast-page and hyper-page mode (EDO) operations is that in the former, the data associated with a previous column access is destroyed when CAS transitions to a high logic level while, in the latter, the data from the previous cycle is not destroyed until CAS begins to transition again from a high logic level to a low logic level. Nonetheless, it is to be appreciated that the time interval tAA is the time parameter which limits the ability to increase the frequency of CAS occurrences (i.e., CAS frequency) and, therefore, limits the data bandwidth realizable in these particular modes of operation.
More recently, an alternative mode of operation has been developed which is known as pipelined nibble mode (referred hereinafter as PNM). PNM operation, also referred to as burst EDO, is a mode of operation which involves pipelined read access of a particular DRAM device. The major difference between fast-page mode or hyper-page mode and PNM is that in the former, data is available on the DQ lines (or retrievable from the DQ lines) before the next column access (i.e., before the occurrence of the next CAS transition to a low logic level) while in PNM or burst EDO mode, there exists a latency period which dictates that data is not provided to be read externally (from the DQ lines) until some time after the second low logic level CAS, e.g., before the third CAS low occurrence. Such a CAS latency allows for pipelining and, thus, much higher CAS frequencies (i.e., greater than approximately 100 Megahertz).
Referring to FIG. 2, a timing diagram illustrates an example of PNM operation. Particularly, similar to EDO mode operation, a single row address is decoded thereby activating that row of memory locations upon the transition of RAS from a high logic level to a low logic level. Next a first column address is presented and decoded in accordance with the first occurrence of a low logic level transition of CAS; however, unlike EDO mode, the data is not placed on the external DQ lines until the second CAS occurrence. Further, as shown in FIG. 2, the data is not destroyed on (i.e., lost from) the DQ lines until the third transition of CAS to a low logic level and, thereafter, data is continuously provided for a fixed number of CAC cycles (i.e., burst of several data words). While a burst of only two data words is depicted in FIG. 2, it is to be understood that PNM will support higher quantities of words per burst (e.g., four, eight, etc.). Also, after a burst of n words, a new (random) column address must be presented to the device at the nth CAS occurrence.
Several advantages flow from such PNM operation. First, as shown in FIG. 2, one column access (CAS transition to low logic level) yields a multiple word burst. However, even more significant is the fact that because data is not required on the external DQ lines until after the second CAS occurrence. This allows a significantly longer time interval tAA within which to operate. As a result of the longer time interval tAA, pipeline stages can be formed to increase CAS frequency.
On the other hand, SDRAM device technology has also attempted to optimize memory access cycles while working within the confines of uniform clock periods defined by a system clock which provides memory access synchronization. A typical manner in which SDRAM devices operate is as follows. A column address is presented and decoded in the first clock period. Within the next clock period, the decoded address is utilized to bring up (activate) appropriate column select lines and sense the addressed memory locations. In the third clock period, the decoded address is used to actually retrieve the data from the appropriate memory locations and place such data on the DQ lines.
While it requires three clock periods before the SDRAM device outputs data, each period thereafter yields data, thus, providing a continuous data output. Similar to PNM operation in DRAM devices, a longer time interval tAA would be possible which would allow for pipeline operation in order to get continuous (burst) data out after the first memory access propagates through the memory device.
However, in order to achieve the above-described benefits associated with optimizing memory access cycles in cooperation with the latency associated with data (DQ) validation after two or more CAS cycles (referred to hereinafter as CAS latency), it would be necessary to include additional pipestage circuitry, latches and other DRAM and SDRAM specific control logic to the memory device, itself, and/or to the associated controlling circuitry. For example, with respect to SDRAM devices, each pipe stage ideally would have to be of the same duration and, further, independent registers would have to be provided between each stage of the process in order to save the results associated with each stage. It is to be appreciated that such additional circuitry added to either DRAM or SDRAM devices would have the adverse effect of increasing chip size and therefore costs associated with the dynamic memory device.
Therefore, there exists a need in the prior art for methods and apparatus for increasing the data bandwidth of dynamic memory devices which, in particular, exploits the advantages of CAS latency and which may be implemented with little or no additional circuitry.
It is an object of the present invention to provide efficient implementation of PNM operation in state of the art EDO DRAMs. Proposed approaches may also find application in efficient realization of SDRAMs.
It is another object of the present invention to provide methods and apparatus for increasing data bandwidth of a dynamic memory device by utilizing an address transition detection pulse to form a pipeline stage.
It is yet another object of the present invention to provide methods and apparatus for increasing data bandwidth of a dynamic memory device by utilizing existing logic circuitry and signals (e.g., already available latches) to form a pipeline stage.
It is still a further object of the present invention to provide methods and apparatus for increasing data bandwidth of a dynamic memory device by temporarily overlapping pipeline stages to provide a wavepipe operation.
It is still a further object of the present invention to provide methods and apparatus for increasing the data bandwidth of a dynamic memory device, and for decreasing power dissipation by the same, by providing segmented column decoding for least significant bits of a column address.
In accordance with one form of the present invention, a method of substantially increasing the data bandwidth of a dynamic memory device is provided, whereby the dynamic memory device includes at least one storage cell, a column decoder and an internal read/write data bus and whereby the column decoder decodes a column address upon receipt thereof such that data stored in the at least one storage cell corresponding to the decoded column address is placed on the internal read/write data in response to the receipt of an address transition detection (ATD) pulse generated by the dynamic memory device. The method includes the step of temporarily suppressing the generation of the ATD pulse such that data selected from the at least one storage cell is not placed on the internal read/write data bus until after a delayed generation of the ATD pulse. In this manner, a first pipeline stage is advantageously formed which essentially includes the presentation of the column address and decoding thereof. Preferably, the delayed ATD pulse is generated in response to the falling edge of a column address strobe (CAS) signal.
Furthermore, the dynamic memory device further preferably includes output data storage means whereby output data is stored in the output data storage means in response to a transfer pulse and wherein the method of the present invention further includes generating the transfer pulse in substantially close time proximity to the generation of the delayed ATD pulse in order to store data already present on the internal read/write data bus, from previously presented column address, in the output data storage means. In this manner, a second pipeline stage is advantageously formed which includes the generation of the transfer pulse and the storage of the data on the internal read/write data bus in the output data storage means. In one embodiment, the transfer pulse is generated in response to the next falling edge of the CAS signal (i.e., the next falling edge of CAS following the falling edge of CAS which generated the delayed ATD pulse) and, still further, the output data storage means is an off chip driver (OCD) latch. Also, each transfer pulse is preferably delayed with respect to the generation of each delayed ATD pulse in order to realize an overlapping of the first and second pipeline stages, described above, for a period of time. Such overlapping of pipeline stages is referred to as wavepipe behavior.
In another embodiment, the dynamic memory device is a DRAM device initially configured to operate in an extended data output (EDO) mode. Accordingly, by temporarily suppressing the generation of the ATD pulse and by generating the transfer pulse, in the manner explained above, such that the first pipeline stage is defined as decoding the first column address prior to the generation of the delayed ATD pulse and the second pipeline stage is defined as the generation of the transfer pulse and storage of the first pipeline data corresponding to the first column address, it is to be appreciated that pipelined nibble mode operation is substantially realized in the EDO DRAM device.
The present invention also provides for the generation of a single I/O enable signal in the dynamic memory device to commonly enable/disable the off chip drivers (OCDs) whether the memory device is operating in a EDO or PNM mode. Still further, the present invention provides a column decoding technique whereby the column decoder includes segment select line column predecoders located in close proximity to a next decoding stage such that at least two consecutive address bits of the column address are provided to the predecoders. Preferably, due to the frequent toggling of the first two least significant bits of a column address in PNM operation, such first two least significant bits of the column address are provided to the segment select line column predecoders for segmented predecoding. In this manner, due to the fact that the segment select line column predecoders are in close proximity to their corresponding next decoding stage, shorter column predecoded address lines are provided therebetween resulting in lower capacitance on these lines and, therefore, a reduction in power dissipation realized by the dynamic memory device.
Thus, the present invention teaches methods and apparatus for increasing the data bandwidth of dynamic memory devices by forming discrete pipeline stages in existing standard dynamic memory devices by exploiting existing control signals, timing behavior and control circuitry. In this manner, it is to be appreciated that little or no additional control circuitry is required to implement the teachings of the present invention and, as a result, the present invention provides for increased CAS frequency which advantageously yields a substantial increase in the data bandwidth associated with the dynamic memory device.